Silicon Power

言語をお選びください

Asia/Pacific
  • AustraliaAustralia
    English
  • BangladeshBangladesh
    English
  • CambodiaCambodia
    English
  • ChinaChina
    中文 (简体)
  • HongKongHongKong
    中文 (繁體)
  • IndiaIndia
    English
  • IndonesiaIndonesia
    English
  • JapanJapan
    日本語
  • KoreaKorea
    English
  • MalaysiaMalaysia
    English
  • MongoliaMongolia
    English
  • MyanmarMyanmar
    မြန်မာ
  • NepalNepal
    English
  • New ZealandNew Zealand
    English
  • PakistanPakistan
    English
  • PhilippinesPhilippines
    English
  • SingaporeSingapore
    English
  • SriLankaSriLanka
    English
  • TaiwanTaiwan
    中文 (繁體)
  • ThailandThailand
    English
  • VietnamVietnam
    Tiếng Việt
Europe
  • AustriaAustria
    Deutsch
  • BelarusBelarus
    Pусский
  • BelgiumBelgium
    Dutch
  • BosniaBosnia
    English
  • BulgariaBulgaria
    English
  • CroatiaCroatia
    English
  • CyprusCyprus
    English
  • Czech RepublicCzech Republic
    English
  • DenmarkDenmark
    English
  • EstoniaEstonia
    English
  • FinlandFinland
    English
  • FranceFrance
    Français
  • GermanyGermany
    Deutsch
  • GreeceGreece
    English
  • HungaryHungary
    English
  • IcelandIceland
    English
  • IrelandIreland
    English
  • ItalyItaly
    Italiano
  • KazakhstanKazakhstan
    Pусский
  • KosovoKosovo
    English
  • LatviaLatvia
    English
  • LithuaniaLithuania
    English
  • MacedoniaMacedonia
    English
  • MaltaMalta
    English
  • NetherlandsNetherlands
    Dutch
  • NorwayNorway
    English
  • PolandPoland
    Polski
  • PortugalPortugal
    English
  • RomaniaRomania
    English
  • RussiaRussia
    Pусский
  • SerbiaSerbia
    English
  • SlovakiaSlovakia
    English
  • SloveniaSlovenia
    English
  • SpainSpain
    Español
  • SwedenSweden
    English
  • SwitzerlandSwitzerland
    Deutsch
  • TurkeyTurkey
    Türkçe
  • UkraineUkraine
    English
  • United KingdomUnited Kingdom
    English
North America
  • CanadaCanada
    English
  • United StatesUnited States
    English
Latin America
  • ArgentinaArgentina
    Español
  • BoliviaBolivia
    Español
  • BrasilBrasil
    English
  • ChileChile
    Español
  • ColombiaColombia
    Español
  • Costa RicaCosta Rica
    Español
  • Dominican RepublicDominican Republic
    Español
  • EcuadorEcuador
    Español
  • El SalvadorEl Salvador
    Español
  • GuatemalaGuatemala
    Español
  • HondurasHonduras
    Español
  • MéxicoMéxico
    Español
  • PanamaPanama
    Español
  • ParaguayParaguay
    Español
  • PeruPeru
    Español
  • UruguayUruguay
    Español
  • VenezuelaVenezuela
    Español
Middle East/Africa
  • AlgeriaAlgeria
    English
  • EgyptEgypt
    English
  • IsraelIsrael
    English
  • KenyaKenya
    English
  • LebanonLebanon
    English
  • LibyaLibya
    English
  • MauritiusMauritius
    English
  • MoroccoMorocco
    Français
  • Saudi ArabiaSaudi Arabia
    English
  • South AfricaSouth Africa
    English
  • TunisiaTunisia
    English
  • UAEUAE
    English
  • YemenYemen
    English
Others
  • OthersOthers
    English
Dr

COMPREHENSIVE WEAR LEVELING MECHANISMS
FOR SP INDUSTRIAL SD AND microSD CARDS

1. INTRODUCTION
For today’s NAND flash devices, the main limitation is Program/Erase lifespan (number of P/E cycles). The key solution for this constraint is tomanage the attrition rate in the entire NAND flash device so that each block will be evenly distributed. Therefore, efficient management of wearin whole blocks is required in order to maximize the lifespan of a NAND flash device. To accomplish this, one method is to manage the P/E cycleof each block individually, which will help to regularly distribute them and avoid overlaying on some blocks. This method is called wear leveling.There are two primary wear leveling mechanisms embedded in the flash translation layer (FTL) – static and dynamic.
2. FTL AND WEAR LEVELING
Wear leveling is implemented in the flash translation layer (FTL), which is the inter-medium mechanism between the file system and the NANDflash device. The FTL provides the mapping rules from logical to physical addressing. Wear leveling will help to reduce the wearing out of blocksover the mapping rules. As shown in Figure 1.
Figure
1

Wear Leveling in the FTL

3. FLASH BLOCK MANAGEMENT
The NAND flash device can be divided into three portions. The data block is reserved for logical capacity, the free block is assigned to wear leveling and bad block pool management, and the system block is assigned to the mapping table, cache block, etc. As shown in Figure 2.
Figure
2

Flash Block Management

4. WEAR LEVELING
4-1 DYNAMIC WEAR LEVELING
There are two types of data subset in a NAND flash device: static data and dynamic data. Static data is information that is rarely used and seldom changed in physical blocks. On the other hand, dynamic data is frequently changing and constantly reprogramed. Dynamic wear leveling allocates dynamic data to the free blocks that have had the fewest P/E cycles. It is easier to implement this method, but in order to optimize the entire flash device completely, it is not a comprehensive technique. As shown in Figure 3.
Figure
3

Dynamic Wear Leveling

4-2 STATIC WEAR LEVELING
Static wear leveling considers an entire NAND flash die, including blank areas and blocks to which have already been written. Static wear leveling allocates static data to the free block; as such, it enables liquidity of the flash device. It can amend the bottlenecking of overall wear leveling and get more efficient usage of memory array, therefore maximizing the lifespan of the flash device. As shown in Figure 4.
Figure
4

Static Wear Leveling

4-3 GLOBAL WEAR LEVELING
As opposed to static wear leveling, which only works on a single NAND flash die, the scope of global wear leveling covers the entire device. This ensures that write behavior occurs in blocks that are written to less frequently throughout the entire device. It achieves this balance by separating the flash device into several zones. If the host continues to access the same zone repeatedly, that zone is likely to wear out more quickly. Global wear leveling intervenes to prevent this from happening by re-allocating that access and ensuring an even level of wearing out. As shown in Figure 5.
Figure
5

Global Wear Leveling

Figure
6

Comparison of Different Wear Leveling Mechanisms

5. SP INDUSTRIAL OFFERINGS FOR INDUSTRIAL SD AND microSD CARDS
SP Industrial’s SD card series SDI730/530/330 and microSD card series SDT730/530/330 are comprehensively equipped with all of these mechanisms: global wear leveling, static wear leveling, and dynamic wear leveling. This multi-faceted coverage to manage all of the different statuses of flash usage achieves the best endurance and the highest reliability for optimized performance of the NAND flash.
SP Industrial’s microSD card series SDT550/350 is equipped with static and dynamic wear leveling mechanisms. It offers the option for higher capacity with 3D TLC, but without the compromise of P/E cycle endurance.
These series are wildly adopted by critical applications, including dash camera surveillance video recording and Telematics systems for tier-1 automotive vendors, data log systems for Telecom 4G/5G base stations, and patient data recording for medical ventilator equipment in hospital ICUs.